1. Field of the Invention
The present invention relates to semiconductor memory devices, and more specifically to a voltage phase generator for driving booster circuits of a memory device.
2. Description of Related Art
Integrated circuits, and especially memory circuits, use booster circuits to raise the voltage over the supply voltage for applications such as the driving of memory arrays word lines. Such booster circuits operate by capacitively charging internal nodes with multiple voltage signals that have a determined time sequence. The voltage signals have the same amplitude but a different phase shift, so they are commonly defined as voltage phases. The voltage phases are generated by appropriate voltage phase generators. For such a purpose, a voltage phase generator typically generates four voltage phases: two phases with an amplitude equal to the supply voltage, and two phases with a greater amplitude that is obtained through a voltage boosting circuit or "bootstrap". Usually, such a greater amplitude amounts to nearly twice the amplitude of the supply voltage. The voltage phases with a raised voltage are known as "boosted" voltage phases.
FIG. 1a shows a conventional voltage phase generator 4. A temporary memory circuit or bi-stable latch LTH is controlled by control signals ST1 and ST2 to pace a normal voltage phase FX (i.e., a signal having the amplitude of the supply voltage VDD) and a negated normal voltage phase FN (i.e., in phase opposition to the normal voltage phase FX). The voltage boosting circuits or bootstraps BT produce a boosted voltage phase FBX (i.e., having a greater amplitude than the supply voltage VDD) and a negated boosted voltage phase FBN from the normal voltage phase FX and negated normal voltage phase FN.
The advancement of the normal voltage phase FX and negated normal voltage phase FN towards the voltage boosting circuits BT is paced by a clock signal CK and a negated clock signal CKN, which are the main clocks of the integrated circuit. The four voltage phases described above are shown in FIGS. 2a and 2b. The voltage phase generator 4 drives a booster circuit 1, which is shown in greater detail in FIG. 1b. The booster circuit 1 has two stages S1 and S2 that receive a supply voltage signal at an input IN and supply a boosted voltage signal from an output OUT. The booster circuit 1 may contain several stages that subsequently raise the voltage up to the desired value. The booster circuit 1 is substantially driven by the four voltage phases FX, FN, FBX, and FBN generated by the voltage phase generator 4 of FIG. 1a.
Both of the normal voltage phases FX and FN are generally subject to high current demands during charge transfers from one stage to the next in the booster circuit 1. In contrast, the boosted voltage phases are primarily used to avoid threshold effects of transfer transistors M1 and M2, which are responsible for charge transfer from one stage to the next. Conventionally, high currents are achieved by interposing driving stages 5 having high driving capacity on the normal voltage phases FX and FN that exit the voltage phase generator 4. In other words, the circuit has driving stages 5 capable of supplying high current and formed by adequately-sized inverter circuits (i.e., with a high channel width to length or aspect ratio) that are capable of supplying the high current.
However, such aspect ratios tend to increase the peak current consumed by the inverter circuit during switching. Besides increasing consumption of the inverter circuit, this can also generate unwanted supply noise. Therefore, there is a drawback to using such inverter circuits in the inability to independently increase the aspect ratio of the transistors of the inverters to comply with any driving capacity requirements because the current consumed during switching also increases.